Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 720

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.

The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9 bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode
(Master or Slave).

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters determine the edges
of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting
in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same
parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.

0

0

1

1

0

0

2

1

1

3

1

0

6

SCK

(CPOL = 0)

SCK

(CPOL = 1)

MOSI

SPI Master ->TXD

SPI Slave -> RXD

NSS

SPI Master -> RTS

SPI Slave -> CTS

SCK cycle (for reference)

MSB

MSB

LSB

LSB

6

6

5

5

4

4

3

3

2

2

1

1

1

2

3

4

5

7

8

6

MISO

SPI Master ->RXD

SPI Slave -> TXD