HP A2Y15AV Manuale Utente

240

Datasheet, Volume 2

This register defines the BIN timing parameters for safe logic – tRCD, tRP, tCL, tWCL 
and tRAS.

31:24

RO

0h

23:16

RW-L

14h

Uncore

tRAS in DCLK cycles (tRAS) 
Minimum ACT to PRE timing Range is 10 to 40 DCLK cycles 

15:12

RW-L

6h

Uncore

Write CAS latency in DCLK cycles (tWCL) 
Delay from CAS WR command to data valid on DDR pins. Range 

is 5–15. The value 5 should not be programmed if the DEC_WRD 

bit in TC_RWP register is set. 

11:8

RW-L

6h

Uncore

CAS latency in DCLK cycles (tCL)
This field is the Delay from CAS command to data out of DDR 

pins. 
This does not define the sample point in the IO. This is defined by 

training in round-trip register and other registers, because this is 

also affected by board delays.
Delay from CAS command to data out of DDR pins. Range is 5–

15. 

1.

This does not define the sample point in the IO. This is 

defined by training in round-trip register and other 

registers, because this is also affected by board delays.

2.

The range of 12–15 is not yet defined by JEDEC, will be 

tested only when such definition will exist. 

7:4

RW-L

6h

Uncore

tRP in DCLK cycles (tRP) 
PRE to ACT same bank delay range is 4–15 DCLK cycles  

3:0

RW-L

6h

Uncore

tRCD in DCLK cycles (tRCD) 
ACT to CAS (RD or WR) same bank delay tRCD range is between 

4 and 15.