HP A2Y15AV Manuale Utente

Processor Configuration Registers

242

Datasheet, Volume 2

2.13.3

SC_IO_LATENCY_C0—IO Latency configuration Register

This register identifies the I/O latency per rank, and I/O compensation (global).

2.13.4

TC_SRFTP_C0–Self Refresh Timing Parameters Register

This register is for the Self-refresh timing parameters.

B/D/F/Type:

0/0/0/MCHBAR MC0

Address Offset:

4028–402Bh

Reset Value:

000E0000h

Access:

RW-L

Size:

32 bits

BIOS Optimal Default

00h

Bit

Access

Reset

Value

RST/

PWR

Description

31:22

Reserved (RSVD)

21:16

RW-L

0Eh

Uncore

Round trip – I/O compensation (RT_IOCOMP)

15:12

RW-L

Uncore

IO latency Rank 1 DIMM 1 (IOLAT_R1D1)

11:8

RW-L

Uncore

IO latency Rank 0 DIMM 1 (IOLAT_R0D1)

7:4

RW-L

Uncore

IO latency Rank 1 DIMM 0 (IOLAT_R1D0)

3:0

RW-L

Uncore

IO latency Rank 0 DIMM 0 (IOLAT_R0D0)

B/D/F/Type:

0/0/0/MCHBAR MC0

Address Offset:

42A4–42A7h

Reset Value:

0100B200h

Access:

RW-L

Size:

32 bits

BIOS Optimal Default

Bit

Access

Reset

Value

RST/

PWR

Description

31:28

RW-L

Uncore

(tMOD)
This field is the time between MRS command and any other

command in DCLK cycles.
Actual value is 8 + programmed-Value. For example, when

programming 4 in the field, tMOD value is actually 12 DCLK

cycles

27:26

Reserved (RSVD)

25:16

RW-L

100h

Uncore

(tZQOPER)
Defines the period required for ZQCL after SR exit

15:12

RW-L

Uncore

(tXS_offset)
Delay from SR exit to the first DDR command
tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.

Range is between 3 and 11 DCLK cycles.

11:0

RW-L

200h

Uncore

(tXSDLL)
Delay between DDR SR exit and the first command that requires

data RD/WR from DDR is in the range of 128 to 1024 DCLK

cycles, though all JEDEC DDRs assume 512 DCLK cycles