HP A2Y15AV Manuale Utente

Datasheet, Volume 2

241

Processor Configuration Registers 

Thie register is for the regular timing parameters in DCLK cycles.

31:30

RW-L

10b

Uncore

1n 2N or 3N selection (CMD_stretch) 
This field defines the operation mode of the command.
00 = N operation
10 = 2N operation
11 = 3N operation 

29

RW-L

0b

Uncore

Command 3-state options (CMD_3st) 
This bit defines when command & address bus is driving.
0 = Drive when channel is active. Tri-stated when all ranks are in 

CKE-off or when memory is in SR or deeper.

1 = Command bus is always driving. When no new valid 

command is driven, previous command & address is driven 

28:24

RW-L

06h

Uncore

tWR in DCLK cycles (tWR) 
Write recovery time. The range is 5 to 16 DCLK cycles. 

23:16

RW-L

10h

Uncore

tFAW in DCLK cycles (tFAW) 
Four-activate window is the time frame in which maximum of 4 

ACT commands to the same rank are allowed. The minimum 

value is 4*tRRD, whereas the maximum value is 63 DCLK cycles.

15:12

RW-L

4h

Uncore

tWTR in DCLK cycles (tWTR) 
Delay from internal WR transaction to internal RD transaction. 

The minimum delay is 4 DCLK cycles, whereas the maximum 

delay is 8 DCLK cycles. 

11:8

RW-L

3h

Uncore

tCKE in DCLK cycles (tCKE) 
CKE minimum pulse width in DCLK cycles. The minimum value is 

3 DCLK cycles, whereas the maximum value is the actual value of 

tXP. 

7:4

RW-L

4h

Uncore

tRTP in DCLK cycles (tRTP) 
Minimum delay from CAS-RD to PRE. The minimum delay is 4 

DCLK cycles, whereas the maximum delay is 8 DCLK cycles. 

3:0

RW-L

4h

Uncore

tRRD in DCLK cycles (tRRD) 
tRRD is the minimum delay between two ACT commands 

targeted to different banks in the same rank. The minimum delay 

is 4 DCLK cycles, whereas the maximum delay is 7 cycles.