HP A2Y15AV Manuale Utente

Datasheet, Volume 2

57

Processor Configuration Registers 

This register allows for enabling/disabling of PCI devices and functions that are within 
the processor package. The following table bit definitions describe the behavior of all 
combinations of transactions to devices controlled by this register. 

All the bits in this register are Intel TXT Lockable.

2

RO

0h

1

RW-L

0b

Uncore

IGD VGA Disable (IVD) 
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, 

the Sub-Class Code within Device 2 Class Code register is 

00.

1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory 

and I/O), and the Sub- Class Code field within Device 2 

Function 0 Class Code register is 80.

BIOS Requirement: BIOS must not set this bit to 0 if the GMS 

field (bits 7:3 of this register) pre-allocates no memory.
This bit MUST be set to 1 if Device 2 is disabled either using a 

fuse or fuse override (CAPID0_A[IGD] = 1) or using a register 

(DEVEN[3] = 0).
This register is locked by Intel TXT lock.
0 = Enable
1 = Disable

0

RW-KL

0b

Uncore

GGC Lock (GGCLCK) 
When set to 1b, this bit will lock all bits in this register.

31:15

RO

0h

14

RW

0b

Uncore

Chap Enable (D7EN) 
0 = Bus 0 Device 7 is disabled and not visible.
1 = Bus 0 Device 7 is enabled and visible.
Non-production BIOS code should provide a setup option to 

enable Bus 0 Device 7. When enabled, Bus 0 Device 7 must be 

initialized in accordance to standard PCI device initialization 

procedures.

13

RW-L

1b

Uncore

PEG60 Enable (D6F0EN) 
0 = Bus 0 Device 6 Function 0 is disabled and hidden.
1 = Bus 0 Device 6 Function 0 is enabled and visible.
This bit will be set to 0b and remain 0b if PEG60 capability is 

disabled.

12:8

RO

0h