Freescale Semiconductor MPC5200B ユーザーズマニュアル

General Purpose I/O (GPIO)

MPC5200B Users Guide, Rev. 1

Freescale Semiconductor

7-47

7.3.2.2

WakeUp GPIO Registers—MBAR+0x0C00

The WakeUp GPIO Register Set provides GPIO control for the 8 WakeUp GPIO pins. These pins are scattered throughout the pin groups, but
are all controlled in this module. It should be noted that WakeUp GPIO can operate as Simple Interrupt GPIO. Because of this, there are
separate registers to enable these pins as Wakeup interupts and/or Simple Interrupts. The distiniction between these two types of interrupts is
made according to the powered state of MPC5200B.

•

In Deep Sleep mode, the WakeUp Interrupt enables are used.

•

In all other modes, the Simple Interrupt enables are used.

In either of the above types of interrupts, we are referring to the WakeUp GPIO and the registers in this module. These are not to be confused
with the Simple Interrupt GPIO pins, which are controlled in the previous module, GPIO Standard.

This WakeUp GPIO register set uses 10 32-bit registers. These registers are located at an offset from MBAR of 0x0C00. Register addresses
are relative to this offset. Therefore, the actual register address is:

MBAR + 0x0C00 + register address

Hyperlinks to the WakeUp GPIO registers are provided below:

7.3.2.2.1

GPW WakeUp GPIO Enables Register—MBAR + 0x0C00

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GPW WakeUp GPIO Enables Register

(0x0C00)

•

GPW WakeUp GPIO Individual Interrupt Enable Register

(0x0C14)

•

GPW WakeUp GPIO Open Drain Emulation Register