Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-58
Freescale Semiconductor
Functional Description
10.4.5.1
Reads from Local Memory
MPC5200B can provide continuous data to a PCI master using two 32-byte buffers. The PCI controller bursts reads internally at each 32-byte
PCI address boundary. The data is stored in the first 32-byte buffer until either the PCI master flushes the data or the transaction terminates
(FRAME deasserts). For prefetchable memory (BAR1 space), the next line can be fetched from memory in anticipation of the next PCI request
(speculative read) and stored in the second buffer. Prefetching is performed for BAR1-addressed transactions if the PCI command is a
Memory-Read-Multiple or the prefetch bit is set in the
PCI address boundary. The data is stored in the first 32-byte buffer until either the PCI master flushes the data or the transaction terminates
(FRAME deasserts). For prefetchable memory (BAR1 space), the next line can be fetched from memory in anticipation of the next PCI request
(speculative read) and stored in the second buffer. Prefetching is performed for BAR1-addressed transactions if the PCI command is a
Memory-Read-Multiple or the prefetch bit is set in the
.
10.4.5.2
Local Memory Writes
A 32-byte write buffer is implemented to improve data throughput. This allows a write operation to be “posted”, that is to successfully
complete even when the PCI internal controller is requesting access to the local memory. In other words, data is latched while waiting for
internal access to local memory to complete. While PCI burst transactions are accepted, writes are sent out on the internal bus as single-beat.
complete even when the PCI internal controller is requesting access to the local memory. In other words, data is latched while waiting for
internal access to local memory to complete. While PCI burst transactions are accepted, writes are sent out on the internal bus as single-beat.
NOTE
Before a read from XL Bus to PCI or PCI to XL Bus can complete, all posted writes are flushed.
If the PCI controller aborts the transaction in the middle of PCI burst due to internal conflicts, the external master recognizes some of the data
as transferred. (Subsequent transfers of a burst will be aborted on PCI bus). The external PCI master must query the “Target abort signalled”
bit in the PCI Type 00h configuration status register to determine if a target abort occurred.
as transferred. (Subsequent transfers of a burst will be aborted on PCI bus). The external PCI master must query the “Target abort signalled”
bit in the PCI Type 00h configuration status register to determine if a target abort occurred.
10.4.5.3
Data Translation
The XL bus supports misaligned operations, however, it is strongly recommended that software attempt to transfer contiguous code and data
where possible. Non-contiguous transfers degrade performance.
where possible. Non-contiguous transfers degrade performance.
PCI-to-XL Bus transaction data translation is shown in
.
Table 10-11. Aligned PCI to XL bus Transfers
PCI Bus
XL bus
BE
[3:0]
AD[2:0]
31:24
23:16
15:8
7:0
A[29:31]
Data Bus Byte Lanes
0
1
2
3
4
5
6
7
1110
000
OP3
000
OP3
1101
000
OP3
001
OP3
1011
000
OP3
010
OP3
0111
000
OP3
011
OP3
1110
100
OP3
100
OP3
1101
100
OP3
101
OP3
1011
100
OP3
110
OP3
0111
100
OP3
111
OP3
1100
000
OP3
OP2
000
OP2
OP3
1001
000
OP3
OP2
001
OP2
OP3
0011
000
OP3
OP2
010
OP2
OP3
1100
100
OP3
OP2
100
OP2
OP3
1001
100
OP3
OP2
101
OP2
OP3
0011
100
OP3
OP2
110
OP2
OP3
1000
000
OP3
OP2
OP1
000
OP1
OP2
OP3
0001
000
OP3
OP2
OP1
000
OP1
OP2
OP3
1000
100
OP3
OP2
OP1
100
OP1
OP2
OP3
0001
100
OP3
OP2
OP1
101
OP1
OP2
OP3
0000
000
OP3
OP2
OP1
OP0
000
OP0
OP1
OP2
OP3
0000
100
OP3
OP2
OP1
OP0
100
OP0
OP1
OP2
OP3