Freescale Semiconductor MPC5200B ユーザーズマニュアル
XLB Arbiter Registers—MBAR + 0x1F00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
16-3
16.1.1.4.2
Other Tenure Ending Conditions
In addition to the watchdog timers, this function will terminate tenures with or without TEA depending on the following conditions:
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AACK the address tenure for eciwx and ecowx transfer types, then TEA the ensuing data tenure. This sets the External Control
Word Read/Write Status bit in the Arbiter Status Register.
Word Read/Write Status bit in the Arbiter Status Register.
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AACK the address tenure for address only and reserved transfer types. (no ensuing data tenure) This sets the TT Address Only Status
bit or TT Reserved Status Bit, respectively, in the Arbiter Status Register.
bit or TT Reserved Status Bit, respectively, in the Arbiter Status Register.
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AACK the address tenure for invalid TBST/TSIZ combinations, then TEA the ensuing data tenure. This sets the TBST/TSIZ
Mismatch Status bit in the Arbiter Status Register.
Mismatch Status bit in the Arbiter Status Register.
If enabled, an interrupt will be issued when a status bit is set.
When the arbiter ends a tenure or detects a TEA from a device, certain bus signals (Address, TT, TSIZ, TBST, GLB) are latched into the
Arbiter Address Capture Register and Arbiter Bus Signal Capture Register. Additional errors will be handled but the original error related
information is maintained until the error status is cleared.
Arbiter Address Capture Register and Arbiter Bus Signal Capture Register. Additional errors will be handled but the original error related
information is maintained until the error status is cleared.
16.2
XLB Arbiter Registers—MBAR + 0x1F00
The XLB Arbiter provides thirteen 32-bit active registers. All registers are located at an offset from the Module Base Address Register
(MBAR). The XLB Arbiter offset from MBAR is 0x1F00. Therefore, the actual address for each XLB Arbiter register is:
(MBAR). The XLB Arbiter offset from MBAR is 0x1F00. Therefore, the actual address for each XLB Arbiter register is:
MBAR + 0x1F00
+ register address.
The read/write nature of each register is shown in the descriptions that follow.
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Bit 0 in all registers is the most significant bit (MSB).
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Reserved bits cannot be written to, and will always read 0.
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Registers may be accessed on the following aligned boundaries:
— 1 byte
— 2 byte
— word (32-bit)
— double-word (64-bit)
— 1 byte
— 2 byte
— word (32-bit)
— double-word (64-bit)
Registers are organized on word boundaries to allow easy register mask operations.
When a bit enables or disables a function, the values are defined as:
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0 = disabled
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1 = enabled
The XLB Arbiter registers are listed below, followed by detailed descriptions of each register.
16.2.1
Arbiter Configuration Register (R/W)—MBAR + 0x1F40
The Arbiter Configuration Register is used to control the arbiter watchdog functionality and other XLB-related system configuration
parameters.
parameters.
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