Microchip Technology MA240029 データシート
PIC24FJ128GA310 FAMILY
DS39996F-page 302
2010-2011 Microchip Technology Inc.
REGISTER 24-2:
AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
PVCFG1
PVCFG0
NVCFG0
OFFCAL
BUFREGEN
CSCNA
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFS
(
SMPI4
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
(
)
ALTS
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
PVCFG<1:0>:
Converter Positive Voltage Reference Configuration bits
1x
= Unimplemented, do not use
01
= External V
REF
+
00
= AV
DD
bit 13
NVCFG0:
Converter Negative Voltage Reference Configuration bits
1
= External V
REF
-
0
= AV
SS
bit 12
OFFCAL:
Offset Calibration Mode Select bit
1
= Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AV
SS
0
= Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
bit 11
BUFREGEN:
A/D Buffer Register Enable bit
1
= Conversion result is loaded into the buffer location determined by the converted channel
0
= A/D result buffer is treated as a FIFO
bit 10
CSCNA:
Scan Input Selections for CH0+ During Sample A bit
1
= Scan inputs
0
= Do not scan inputs
bit 9-8
Unimplemented:
Read as ‘0’
bit 7
BUFS:
Buffer Fill Status bit
(
)
1
= A/D is filling the upper half of the buffer; user should access data in the lower half
0
= A/D is filling the lower half of the buffer; user should access data in the upper half
bit 6-2
SMPI<4:0>:
Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1:
0001
0001
= For 2-channel DMA A/D operation
0000
= For 1-channel DMA A/D operation
When DMAEN = 0:
Selects the number of sample/conversions per each interrupt
Selects the number of sample/conversions per each interrupt
11111
= Interrupt/address increment at the completion of conversion for each 32nd sample
11110
= Interrupt/address increment at the completion of conversion for each 31st sample
00001
00001
= Interrupt/address increment at the completion of conversion for every other sample
00000
= Interrupt/address increment at the completion of conversion for each sample
Note 1:
These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
is only used when BUFM = 1.