Microchip Technology MA240029 데이터 시트
PIC24FJ128GA310 FAMILY
DS39996F-page 228
2010-2011 Microchip Technology Inc.
REGISTER 16-3:
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPIFE
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN:
Framed SPIx Support bit
1
= Framed SPIx support is enabled
0
= Framed SPIx support is disabled
bit 14
SPIFSD:
Frame Sync Pulse Direction Control on SSx Pin bit
1
= Frame sync pulse input (slave)
0
= Frame sync pulse output (master)
bit 13
SPIFPOL:
Frame Sync Pulse Polarity bit (Frame mode only)
1
= Frame sync pulse is active-high
0
= Frame sync pulse is active-low
bit 12-2
Unimplemented:
Read as ‘0’
bit 1
SPIFE:
Frame Sync Pulse Edge Select bit
1
= Frame sync pulse coincides with the first bit clock
0
= Frame sync pulse precedes the first bit clock
bit 0
SPIBEN:
Enhanced Buffer Enable bit
1
= Enhanced buffer is enabled
0
= Enhanced buffer is disabled (Legacy mode)