Microchip Technology MA240029 데이터 시트

 2010-2011 Microchip Technology Inc.

DS39996F-page 229

PIC24FJ128GA310 FAMILY

FIGURE 16-3:

SPI MASTER/SLAVE CONNECTION (STANDARD MODE)

FIGURE 16-4:

SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)

Serial Receive Buffer

(SPIxRXB)

(2)

Shift Register

(SPIxSR)

(2)

LSb

MSb

SDIx

SDOx

Processor 2 (SPI Slave)

SCKx

SSx

(1)

Serial Transmit Buffer

(SPIxTXB)

(2)

Serial Receive Buffer

(SPIxRXB)

Shift Register

(SPIxSR)

MSb

LSb

SDOx

SDIx

Processor 1 (SPI Master)

Serial Clock

SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0

Note 1:

Using the SSx pin in Slave mode of operation is optional.

User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory mapped to SPIxBUF.

SCKx

Serial Transmit Buffer

(SPIxTXB)

MSTEN (SPIxCON1<5>) = 1)

SPIx Buffer

(SPIxBUF)

(2)

SPIx Buffer

(SPIxBUF)

(2)

Shift Register

(SPIxSR)

LSb

MSb

SDIx

SDOx

Processor 2 (SPI Enhanced Buffer Slave)

SCKx

SSx

(1)

Shift Register

(SPIxSR)

MSb

LSb

SDOx

SDIx

Processor 1 (SPI Enhanced Buffer Master)

Serial Clock

SSEN (SPIxCON1<7>) = 1,

Note 1:

Using the SSx pin in Slave mode of operation is optional.

User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are
memory mapped to SPIxBUF.

SSx

SCKx

8-Level FIFO Buffer

MSTEN (SPIxCON1<5>) = 1 and

SPIx Buffer

(SPIxBUF)

(2)

8-Level FIFO Buffer

SPIx Buffer

(SPIxBUF)

(2)

SPIBEN (SPIxCON2<0>) = 1

MSTEN (SPIxCON1<5>) = 0 and

SPIBEN (SPIxCON2<0>) = 1