사용자 설명서차례Table of Contents3Preface71 Introduction91.1 Purpose of the Peripheral91.2 Features91.3 Functional Block Diagram101.4 Industry Standard(s) Compliance Statement102 Peripheral Architecture112.1 Clock Control112.2 Signal Descriptions122.3 Pin Multiplexing122.4 Protocol Description122.5 VLYNQ Functional Description132.5.1 Write Operations142.5.2 Read Operations152.6 Initialization162.7 Auto-Negotiation162.8 Serial Interface Width Configuration162.9 Address Translation172.10 Flow Control202.11 Reset Considerations212.11.1 Software Reset Considerations212.11.2 Hardware Reset Considerations212.12 Interrupt Support212.12.1 Interrupt Events and Requests212.12.2 Writes to Interrupt Pending/Set Register222.12.3 Remote Interrupts232.12.4 Serial Bus Error Interrupts232.13 DMA Event Support232.14 Power Management242.15 Emulation Considerations243 VLYNQ Port Registers253.1 Revision Register (REVID)263.2 Control Register (CTRL)273.3 Status Register (STAT)293.4 Interrupt Priority Vector Status/Clear Register (INTPRI)313.5 Interrupt Status/Clear Register (INTSTATCLR)313.6 Interrupt Pending/Set Register (INTPENDSET)323.7 Interrupt Pointer Register (INTPTR)323.8 Transmit Address Map Register (XAM)333.9 Receive Address Map Size 1 Register (RAMS1)343.10 Receive Address Map Offset 1 Register (RAMO1)343.11 Receive Address Map Size 2 Register (RAMS2)353.12 Receive Address Map Offset 2 Register (RAMO2)353.13 Receive Address Map Size 3 Register (RAMS3)363.14 Receive Address Map Offset 3 Register (RAMO3)363.15 Receive Address Map Size 4 Register (RAMS4)373.16 Receive Address Map Offset 4 Register (RAMO4)373.17 Chip Version Register (CHIPVER)383.18 Auto Negotiation Register (AUTNGO)384 Remote Configuration Registers39Appendix A VLYNQ Protocol Specifications40A.1 Special 8b/10b Code Groups40A.2 Supported Ordered Sets40A.2.1 Idle (/I/)41A.2.2 End of Packet (/T/)41A.2.3 Byte Disable (/M/)41A.2.4 Flow Control Enable (/P/)41A.2.5 Flow Control Disable (/C/)41A.2.6 Error Indication (/E/)41A.2.7 Init0 (/0/)41A.2.8 Init1 (/1/)41A.2.9 Link (/L/)41A.3 VLYNQ 2.0 Packet Format41A.4 VLYNQ 2.X Packets43Appendix B Write/Read Performance45B.1 Write Performance45B.2 Read Performance47Appendix C Revision History48크기: 386킬로바이트페이지: 49Language: English매뉴얼 열기