Motorola MCF5281 用户手册

27-8

MOTOROLA

 

This subsection describes the QADC registers.

The QADCMCR contains bits that control QADC debug and stop modes and determine the
privilege level required to access most registers.

1

S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only 
addresses have no effect and result in a cycle termination transfer error.

0x19_0000

QADC Module Configuration Register (QADCMCR)

S

0x19_0002

QADC Test Register (QADCTEST)

 2

2

Access results in the module generating an access termination transfer error if not in test mode.

S

0x19_0004

Reserved

 3

3

Read/writes have no effect and the access terminates with a transfer error exception.

—

0x19_0006

Port QA Data Register (PORTQA)

Port QB Data Register (PORTQB)

S/U

0x19_0008

Port QA Data Direction Register (DDRQA) Port QB Data Direction Register (DDRQB)

S/U

0x19_000a

QADC Control Register 0 (QACR0)

S/U

0x19_000c

QADC Control Register 1 (QACR1)

S/U

0x19_000e

QADC Control Register 2 (QACR2)

S/U

0x19_0010

QADC Status Register 0 (QASR0)

S/U

0x19_0012

QADC Status Register 1 (QASR1)

S/U

0x19_0014–

0x19_01fe

Reserved

(3)

—

0x19_0200–

0x19_027e

Conversion Command Word Table (CCW)

S/U

0x19_0280–

0x19_02fe

Right Justified, Unsigned Result Register (RJURR)

S/U

0x19_0300–

0x19_037e

Left Justified, Signed Result Register (LJSRR)

S/U

0x19_0380–

0x19_03fe

Left Justified, Unsigned Result Register (LJURR)

S/U

15

14

13

8

Field

QSTOP

QDBG

—

Reset

0000_0000

R/W:

R/W

R