Motorola MCF5281 用户手册
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MCF5282 User’s Manual
MOTOROLA
MCF5282 Key Features
1.1.1
Version 2 ColdFire Core
The processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for
instruction-address generation and instruction fetch. The instruction buffer is a
first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the
operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage
decodes instructions and selects operands (DSOC); the second stage (AGEX) performs
instruction execution and calculates operand effective addresses, if needed.
instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for
instruction-address generation and instruction fetch. The instruction buffer is a
first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the
operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage
decodes instructions and selects operands (DSOC); the second stage (AGEX) performs
instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A with added
support for a separate user stack pointer register and four new instructions to assist in bit
processing. Additionally, the MCF5282 core includes the enhanced multiply-accumulate
unit (EMAC) for improved signal processing capabilities. The EMAC implements a
4-stage execution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit
accumulators. Supported operands include 16- and 32-bit signed and unsigned integers,
signed fractional operands, and a complete set of instructions to process these data types.
The EMAC provides superb support for execution of DSP operations within the context of
a single processor at a minimal hardware cost.
support for a separate user stack pointer register and four new instructions to assist in bit
processing. Additionally, the MCF5282 core includes the enhanced multiply-accumulate
unit (EMAC) for improved signal processing capabilities. The EMAC implements a
4-stage execution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit
accumulators. Supported operands include 16- and 32-bit signed and unsigned integers,
signed fractional operands, and a complete set of instructions to process these data types.
The EMAC provides superb support for execution of DSP operations within the context of
a single processor at a minimal hardware cost.
1.1.1.1
Cache
The 2-Kbyte cache can be configured into one of three possible organizations: a 2-Kbyte
instruction cache, a 2-Kbyte data cache or a split 1-Kbyte instruction/1-Kbyte data cache.
The configuration is software-programmable by control bits within the privileged cache
configuration register (CACR). In all configurations, the cache is a direct-mapped
single-cycle memory, organized as 128 lines, each containing 16 bytes of data. The
memories consist of a 128-entry tag array (containing addresses and control bits) and a
2-Kbyte data array, organized as 512 x 32 bits. The tag and data arrays are accessed in
parallel using the following address bits:
instruction cache, a 2-Kbyte data cache or a split 1-Kbyte instruction/1-Kbyte data cache.
The configuration is software-programmable by control bits within the privileged cache
configuration register (CACR). In all configurations, the cache is a direct-mapped
single-cycle memory, organized as 128 lines, each containing 16 bytes of data. The
memories consist of a 128-entry tag array (containing addresses and control bits) and a
2-Kbyte data array, organized as 512 x 32 bits. The tag and data arrays are accessed in
parallel using the following address bits:
If the desired address is mapped into the cache memory, the output of the data array is
driven onto the ColdFire core's local data bus, completing the access in a single cycle. If
the data is not mapped into the tag memory, a cache miss occurs and the processor core
initiates a 16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used
driven onto the ColdFire core's local data bus, completing the access in a single cycle. If
the data is not mapped into the tag memory, a cache miss occurs and the processor core
initiates a 16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used
Table 1-1. Cache Configuration
Configuration
Tag Address
Data Array Address
2 Kbyte I-Cache
[10:4]
[10:2]
2 Kbyte D-Cache
[10:4]
[10:2]
Split I-/D-Cache 0
Instruction Fetches
Operand Accesses
Instruction Fetches
Operand Accesses
0, [9:4]
1, [9:4]
1, [9:4]
0, [9:2]
1, [9:2]
1, [9:2]