Motorola MCF5281 用户手册
29-24
MCF5282 User’s Manual
MOTOROLA
Background Debug Mode (BDM)
29.5.3.3.2 Write A/D Register (
WAREG
/
WDREG
)
The operand longword data is written to the specified address or data register. A write alters
all 32 register bits. A bus error response is returned if the CPU core is not halted.
all 32 register bits. A bus error response is returned if the CPU core is not halted.
Command Format:
Command Sequence
Figure 29-20.
WAREG
/
WDREG
Command Sequence
Operand Data
Longword data is written into the specified address or data register.
The data is supplied most-significant word first.
The data is supplied most-significant word first.
Result Data
Command complete status is indicated by returning 0xFFFF (with S
cleared) when the register write is complete.
cleared) when the register write is complete.
29.5.3.3.3 Read Memory Location (
READ
)
Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware
forces low-order address bits to zeros for word and longword accesses to ensure that word
addresses are word-aligned and longword addresses are longword-aligned.
forces low-order address bits to zeros for word and longword accesses to ensure that word
addresses are word-aligned and longword addresses are longword-aligned.
15
12
11
8
7
4
3
2
0
0x2
0x0
0x8
A/D
Register
D[31:16]
D[15:0]
Figure 29-19.
WAREG
/
WDREG
Command Format
WAREG/WDREG
???
LS DATA
’NOT READY’
NEXT CMD
’NOT READY’
XXX
BERR
MS DATA
’NOT READY’
NEXT CMD
’CMD COMPLETE’