Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1008
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 45-4. DMA transfer with LOD = 1
summarizes the different cases.
Note:
1. Depending on the mode, there are other ways of clearing the DATRDY flag. See
Warning: In DMA mode, reading to the Output Data registers before the last data transfer may lead to unpredictable results.
DATRDY
Enable DMA Channels associated with TDES_IDATARx and TDES_ODATARx registers
Multiple Encryption or Decryption Processes
BTC / channel 0
Message fully processed
(cipher or decipher)
MAC result can be read
(cipher or decipher)
MAC result can be read
Write accesses into AES_IDATARx
Message fully transferred
Table 45-4. Last Output Data Mode Behavior versus Start Modes
Sequence
Manual and Auto Modes
DMA Transfer
LOD = 0
LOD = 1
LOD = 0
LOD = 1
DATRDY Flag Clearing
Condition
At least one Output
Data Register must be
read
At least one Input Data
Register must be written
Not used
Managed by the DMA
End of
Encryption/Decryption
Notification
DATRDY
DATRDY
2 DMA flags
(BTC[n/m])
DMA flag (BTC[n]) then
AES DATRDY
Encrypted/Decrypted
Data Result Location
In the Output Data
Registers
In the Output Data
Registers
At the address
specified in the
Channel Buffer
Channel Buffer
Transfer Descriptor
In the Output Data
Registers