Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
175
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
21.6
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect
the PLL minimum input frequency when programming the divider.
the PLL minimum input frequency when programming the divider.
Figure 21-4. Divider and PLL Block Diagram
21.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the
respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal
frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is
saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal
frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is
saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or LOCKB) in PMC_SR is
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT or PLLBCOUNT) in CKGR_PLLR
(CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then decrements at the speed of the
Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor.
The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT or PLLBCOUNT) in CKGR_PLLR
(CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then decrements at the speed of the
Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor.
The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.
During the PLLA or PLLB initialization, the PMC_PLLICPR register must be programmed correctly.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
Divider B
DIVB
PLL B
MULB
DIVA
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
OUTB
OUTA
SLCK
PLLACK
PLLBCK
Divider A
PLL B
MAINCK