Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral
clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core.

The Power Management Controller provides all the clock signals to the system.

PMC input clocks:



PLLACK: From PLLA



PLLBCK: From PLLB and dedicated to USB clock generation.



SLCK: slow clock from external 32 kHz oscillator or internal 32 kHz RC



MAINCK: Main Clock from external 16 MHz oscillator or internal 12 MHz RC

PMC output clocks:



Processor Clock PCK.



Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge. The divider can be 2, 
3 or 4. 



Each peripheral embeds its own divider, programmable in the PMC User Interface.



133 MHz DDR system clock

Note:

DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).



LCD pixel clock that can use DDR system clock or MCK, the choice is done in the LCD user interface.



UHP Clock (UHPCK), required by USB Host Port operations.



UDP Clock (UDPCK), required by USB Device Port operations.



Two programmable clock outputs: PCK0 and PCK1

This allows software control of five flexible operating modes:



Normal Mode, processor and peripherals running at a programmable frequency



Idle Mode, processor stopped waiting for an interrupt 



Slow Clock Mode, processor and peripherals running at low frequency



Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for 
an interrupt



Backup Mode, Main Power Supplies off, VDDBU powered by a battery