Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all
the peripherals and the memory controller. 

The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides
a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs.

The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which
allows the processor clock to be faster than the Master Clock.

The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock
Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in
PMC_MCKR programs the prescaler. 

Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until
the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature
is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.

SysClk DDR

MCK 

periph_clk[..]

int

SLCK

MAINCK

PLLACK

Prescaler

/1,/2,/4,.../64

PCK

Processor

Clock 

Controller

Master Clock Controller  

Peripherals

Clock Controller

ON/OFF

/1   /2    /3   /4

SLCK

MAINCK

Prescaler

/1,/2,/4,...,/64

Programmable Clock Controller  

pck[..]

ON/OFF

/1,/2

Divider

X   /1  /1.5  /2

Divider

PLLBCK

PLLBCK