Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1068
Datasheet
15.7.29
iunit_IUNIT_CSI_CONTROL_type (IUNIT_CSI_CONTROL)—
Offset E8h
Control register for MIPI-CSI
Access Method
Default: 000003F8h
27:24
0h
RW
ICSI2_HSRXCLKTRIM:
ICSI2_HSRXCLKTRIM: Delay for CSI2 clock lane. Refer to the
CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value setting.
23:20
0h
RW
ICSI2_HSRXDATATRIM:
ICSI2_HSRXDATATRIM: Delay for CSI2 data lane. Refer to
the CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value
setting.
19:16
0h
RW
ICSI1_HSRXCLKTRIM:
ICSI1_HSRXCLKTRIM: Delay for CSI1 clock lane. Refer to the
CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value setting.
15:0
0h
RW
ICSI1_HSRXDATATRIM:
ICSI1_HSRXDATATRIM: Delay for CSI1 data lanes. Refer to
the CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value
setting.
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 32 bits)
IUNIT_CSI_CONTROL:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0
RSVD_31_20
CS
I_PO
R
TCO
NFIG
RSVD_15_10
CS
I3_A
CTIV
E_LA
NE
S
CS
I2_A
CTIV
E_LA
NE
S
CS
I1_A
CTIV
E_LA
NE
S
CSI3_DIS
ABLE
CSI2_DIS
ABLE
CSI1_DIS
ABLE
Bit
Range
Default &
Access
Description
31:20
0h
RW
RSVD_31_20:
Reserved
19:16
0h
RW
CSI_PORTCONFIG:
CSI_PORTCONFIG: Used to enable the CSI data lanes to CSI ports
if FB_csi_portconfig_override fuse is set. This field is ignored if
FB_csi_portconfig_override fuse is clear.
15:10
0h
RW
RSVD_15_10:
Reserved
9:8
11b
RW
CSI3_ACTIVE_LANES:
Used to determine which of the lanes that are enabled by the
FB_csi_portconfig fuses or the CSI_PORTCONFIG field, are currently being used on the
MIPI CSI3 interface. 1=active, 0=inactive.
7
1b
RW
CSI2_ACTIVE_LANES:
Used to determine which of the lanes that are enabled by the
FB_csi_portconfig fuses or the CSI_PORTCONFIG field, are currently being used on the
MIPI CSI2 interface. 1=active, 0=inactive.
6:3
1111b
RW
CSI1_ACTIVE_LANES:
Used to determine which of the lanes that are enabled by the
FB_csi_portconfig fuses or the CSI_PORTCONFIG field, are currently being used on the
MIPI CSI1 interface. 1=active, 0=inactive.
2
0b
RW
CSI3_DISABLE:
1 = Disable MIPI CSI3 interface. 0 = Enable MIPI CSI3 interface if
FB_csi_portdisable[2] fuse is cleared