Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2041
17.17.20 PCS_DWORD19 (pcs_dword19)—Offset 4Ch
Access Method
Default: 00004F10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
re
se
rv
ed
524
re
g_lr
c_calcs
only
adcou
t_9_8
adcou
t_7_0
adc2_9_2
adc1_9_2
Bit
Range
Default &
Access
Description
31:27
0h
RW
reserved524:
reserved
26
0h
RW
reg_lrc_calcsonly:
Determines whether LRC ADC1/2 sequence will be bypassed when
crireset_l goes from asserted to de-asserted state 0: Full LRC sequence will run (both
ADC1/2 and calculations) 1: Do not run LRC ADC1/2. Only LRC calculations sequence
will run. It is expected that ADC1/2 config registers will be overridden with desired
values when using this mode
25:24
X
RO
adcout_9_8:
ADC Output Value2 Output of the ADC decimination filter; 2 upper bits
out of 10.
23:16
X
RO
adcout_7_0:
ADC Output Value1 Output of the ADC decimination filter; 8 lower bits
out of 10.
15:8
80h
RW
adc2_9_2:
LRC ADC2 Value Values in this register will be used by LRC_FSM to
compute and cancel out IR drop. If register is written prior to LRC cycle, values will be
overridden by FSM. If registers are written after LRC cycle, the original values are
overridden and the new values will be applicable and will be used for subsequent cycle.
7:0
80h
RW
adc1_9_2:
LRC ADC1 Value Values in this register will be used by LRC_FSM to
compute and cancel out IR drop. If register is written prior to LRC cycle, values will be
overridden by FSM. If registers are written after LRC cycle, the original values are
overridden and the new values will be applicable and will be used for subsequent cycle.
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword19:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0
iamp0calc
o
de
_7_0
ca
l_num
cal_star
t
cal_t
ype
cal_in
v
cal_rs
t
calcl
kdivsel_1_0
re
se
rv
ed
525
ca
lib_done
cal_fb
_coun
t
adc_acc
time
_1_0
adc
_
clksel_1_0
adcmuxsel_2_0
ad
cstar
t