Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2043
17.17.22 PCS_DWORD21 (pcs_dword21)—Offset 54h
Access Method
Default: 80808080h
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
rxvgarcc
ode_7_0
rxtermrcc
o
de_7_0
tx
rcc
o
de_7_0
irefrcc
o
de_7_0
Bit 
Range
Default & 
Access
Description
31:24
80h
RW
rxvgarccode_7_0: 
Rx VGA Rcomp Codes These bits are the final binary code used by 
the Rx VGA. This block only uses the X upper MSBs of this value. Writing to this register 
will override the rcomp code to the Rx VGA. An LRC Ready pulse must be generated to 
the Rx VGA target for this value to take effect. [7:n] - compensation code sent to Iref 
[n-1:0] - remaining LSBs from scaling and offset calculation
23:16
80h
RW
rxtermrccode_7_0: 
Rx Termination Rcomp Codes These bits are the final binary code 
used by the Rx termination. This block only uses the 7 upper MSBs of this value. Writing 
to this register will override the rcomp code to Rxterm. An LRC Ready pulse must be 
generated to the Rxterm target for this value to take effect. [7:1] - compensation code 
sent to Rxterm [0] - remaining LSB from scaling and offset calculation
15:8
80h
RW
txrccode_7_0: 
Tx Rcomp Codes These bits are the final binary code used by the Tx. 
This block only uses the 7 upper MSBs of this value. Writing to this register will override 
the rcomp code to the Tx. An LRC Ready pulse must be generated to the Tx target for 
this value to take effect. [7:1] - compensation code sent to Tx [0] - remaining LSB from 
scaling and offset calculation
7:0
80h
RW
irefrccode_7_0: 
Iref Rcomp Codes These bits are the final binary code used by the 
Iref block. This block only uses the 6 upper MSBs of this value. Writing to this register 
will override the rcomp code to the Iref block. An LRC Ready pulse must be generated 
to the Iref target for this value to take effect. [7:2] - compensation code sent to Iref 
[1:0] - remaining LSBs from scaling and offset calculation
Type: 
Message Bus Register
(Size: 32 bits)
pcs_dword21: 
Op Codes:
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
rxvgarc
scal
e_7_0
rx
te
rm
rc
scal
e_7_0
txrc
scal
e_7_0
ir
ef
rc
scal
e_7_0