Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2042

Datasheet

Default: 80808080h

31:24

0h

RW

IREF Opamp Calibration Codes These bits are written by the 

calibration state machine. Bit7 - Calibration enable that configures the target into a 

calibration mode Bit6 - Calibration sign bit Bit[5:0] - Calibration magnitude [lyonel to 

check bit7 functionality].

23:20

0h

RW

Calibration Number or Address numbers of cal targets or address for specific 

cal target if cal_type = 1

19

0h

RW

Calibration Start This bit is used to start a Cal cycle vias IOSF-SB. The cal 

cycle will follow the normal cal cycle as set by cal_num, cal_type, cal_inv and cal_rst. 

The Cal cycle starts when this bit transitions 0 1 1 = Run Cal. 0 = wait (default)

18

0h

RW

Calibration Type Enable calibration of one cal target defined by cal_num 0 = 

multi 1 = single

17

0h

RW

Calibration Feedback Invert Inverse the logic of counter increment decrement 

depends on the FB

16

0h

RW

Calibration Reset Reset state machine

15:14

1h

RW

Calibration Clock Divider Select 00 - div2 of CRICLK 01 - div4 of 

CRICLK 10 - div8 of CRICLK 11 - div16 of CRICLK Note: Calibration clock period target 

is 160nS

13

0h

RO

reserved

12

0h

RO

Calibration Completion Indicator

11:8

Fh

RW

Calibration Cycle Count Limit per target Each calibration target is 

clocked for 16 * cal_fb_count clock cycles. Max is 240 clock cycles (default)

7:6

0h

RW

ADC Accumulation Time Select This selects the conversion time for 

the Analog to Digital Converter. ADC clock frequency is set by bits [5:4] in this register. 

00: 1024 ADC clocks (default) 01: 512 ADC clocks 10: 256 ADC clocks 11: Infinite 

(ADC in continuous accumulation) Note: If LRC mode and set to '11', then adctime = 

1024cycles.

5:4

1h

RW

ADC Clock Frequency Select This selects the input clock frequency to 

the Analog to Digital Converter. 00: CRI clock div2 01: CRI clock div1 10: CRI clock div4 

11: CRI clock div8 NOTE: Target is 50Mhz.

3:1

0h

RW

ADC Analog Mux Select This selects the analog voltage input to the 

Analog to Digital Converter. 000: Vss 001: Vcc 010: LRC R1 voltage divider 011: LRC 

sense net 100: input from Tx 101: input from Rx (or Tx #2) 110: input from Clock 111: 

input from reference generator Note: Mux select is controlled by the FSM during LRC.

0

0h

RW

ADC start This bit resets the ADC counter and starts a new acquisition. This 

bit should remain 1'b1 while the ADC is active and acquiring data. 0: Disable ADC logic 

and analog circuitry 1: Enable ADC and start A2D conversion.

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write