Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2075
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0
re
g_
p
ar
ti
al
re
g_slu
m
b
er
re
g_tx2_
cd
r_o
ve
rr
ide_2_0
re
g_
cd
r_o
ve
rr
ide_2_0
reg_ebu
ffm
ode
reg_u
sedclo
ckch
annel_1_0
re
g
_
us
ed
cl
oc
kc
ha
n
n
el_
ov
rr
ide
reg
_
gb
l_o
vrrid
e
reg_tx1_pclk
on_inp2
reg_tx2_pclk
on_inp2
reg_tx2_tx
enable
cr
i_rx
eb
_ptr_in
it_3_0
re
g
_
powe
rfsm_o
vrrid
e
re
g_sus
p
en
d
reg
_
pcl
kcfgin
p
ut
reg
_
use
q
cl
ock
cr
i_rx
eb
_hiw
ater_3_0
cr
i_rx
eb
_low
ater_3_0
Bit
Range
Default &
Access
Description
31
0h
RW
reg_partial:
Override for i_partial
30
0h
RW
reg_slumber:
Override for i_slumber
29:27
0h
RW
reg_tx2_cdr_override_2_0:
Override for cdr_override strap for second tx2
26:24
0h
RW
reg_cdr_override_2_0:
Override for cdr_override strap
23
0h
RW
reg_ebuffmode:
Override for ebuffmode (no functionality in p1271 phase1 design)
22:21
0h
RW
reg_usedclockchannel_1_0:
Selects the active clock channel
20
0h
RW
reg_usedclockchannel_ovrride:
When asserted selects reg_usedclockchannel[1:0]
19
0h
RW
reg_gbl_ovrride:
Global override select
18
0h
RW
reg_tx1_pclkon_inp2:
When asserted keeps PCLK running in P2 mode. For DP this is
used for Lane1
17
0h
RW
reg_tx2_pclkon_inp2:
When asserted keeps PCLK running in P2 mode. This is
reserved (no impact) for PCIe/DMI and used for DP Lane2
16
0h
RW
reg_tx2_txenable:
Override for i_txenable for tx2
15:12
0h
RW
cri_rxeb_ptr_init_3_0:
Config override for initial value of Rx elastic buffer read
pointer
11
0h
RW
reg_powerfsm_ovrride:
When asserted overrides for Tx power fsm are selected
10
0h
RW
reg_suspend:
Override for suspend
9
0h
RW
reg_pclkcfginput:
Override for pclkcfginput strap
8
0h
RW
reg_useqclock:
Override for useqclock; MUX select for I or Q clk for TX clocking
7:4
Ch
RW
cri_rxeb_hiwater_3_0:
Elastic buffer high watermark based on which SKP is
removed