Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2077
17.19.11 PCS_DWORD10 (pcs_dword10)—Offset 28h
Access Method
Default: 00000000h
12:10
0h
RW
reg_txmargin_2_0:
Override for i_txmargin
9
0h
RW
reg_txswing:
Override for i_txswing
8
0h
RW
reg_txenable:
Override for i_txenable
7:6
0h
RW
reg_txterm_vcc_1_0:
Override for txterm_vcc strap
5
0h
RW
reg_txdetrxlpbk:
Override for i_txdetrxlpbk
4
0h
RW
reg_txelectidle:
Override for i_txelectidle
3
0h
RW
reg_txcompliance:
Override for i_txcompliance
2
0h
RW
reg_txoneszeroes:
Override for i_txoneszeroes
1:0
0h
RW
reg_latencyoptim_1_0:
Override for i_latencyoptim
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword10:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_rxpwrfsm_time
r_W
AIT
_
R
X
_P
I_CLK_3_0
re
g_rxpw
rf
sm
_t
im
er_ENABLE_RX_3_0
reg_rxpwrfsm_time
r_RX
_
SQE
N
_3_0
reg_rxpw
rf
sm_tim
er_W
AIT_RX_PIBIAS_3_0
re
g_
cl
k_v
alid_cnt_7_0
re
g_rxt
erm
re
g_rxp
o
larit
y
re
g_
rx
eq
tr
ai
n
re
g
_
rxsq
ue
lche
n
cr
i_rxpwrfs
m
_sq
en
timer_o
vr
de
n
re
g
_
rxintfl
tren
_
ov
er
ride
re
g_rxin
tfltre
n_l
re
g_c
lk_v
alid
_
cnt_o
vr
d