Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2085
17.19.17 PCS_DWORD16 (pcs_dword16)—Offset 40h
Access Method
Default: 01000001h
13:8
3h
RW
reserved513:
reserved
7:0
0h
RW
reg_clkbuf_stagger_cnt_9_2:
Counter override value for staggering delay of clock
buffer control signals.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword16:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
sq
ue
lch_s
hunt_o
vr
d_e
n
sq
uelch
_
shun
t_cnt_2_0
re
se
rv
ed
520
i_r
xsqfs
m
_
timersel
i_rxs
q
_async
m
ode_h
i_rxs
q
uelchstby_h
re
se
rv
ed
519
cri_dfx_e
venoddmask_1_0
re
se
rv
ed
518
cr
i_dfx_lce2pats
rc_1_0
cri
_
dfx_lcepats
rc_1_0
re
se
rv
ed
517
txloadgen_ctr
_
va
l
cri_txhighpowe
re
i_ovr
d
en
cr
i_tx1highpow
erei_ovrdv
al
cr
i_tx2highpow
erei_ovrdv
al
p2_fast_exit_en
Bit
Range
Default &
Access
Description
31
0h
RW
squelch_shunt_ovrd_en:
Squelch Shunt Pulse Duration Override Enable Overrides
the hardware default shunt pulse duration value 1: Shunt Pulse Duration Override
Enable 0: Shunt Pulse Duration Override Disable
30:28
0h
RW
squelch_shunt_cnt_2_0:
Squelch Shunt Pulse Duration Override Value 000 = No
shunt pulse generated 001 = 1 susclk cycles ... 111 = 7 susclk cycles
27
0h
RW
reserved520:
reserved
26
0h
RW
i_rxsqfsm_timersel:
Squelch FSM Timer Select 0 - Selects 25Mhz values for squelch
timer and shunt pulse generation . 1 - Selects 100Mhz values for squelch timer and
shunt pulse generation. This register is applicable to synchronous squelch startup
mode.
25
0h
RW
i_rxsq_asyncmode_h:
Squelch Async Startup Mode This squelch startup mode is
power state independent. When enabled, the squelchen signal sent to Modphy will
asynchronously enable the squelch detector circuit. Once enabled, the squelch detector
circuit will asynchronously send an unfiltered/unqualified squelch indication signal out
of Modphy. The squelch indication signal will initially be unstable, so it is up to the
consumer of this signal to filter/qualfiy it accordingly. The asynchronous squelch startup
mode is beneficial because it significantly reduces the squelch startup latency. This
decrease in latency does come at the cost of slightly higher power when squelch is not
enabled as the IREF and Squelch Keeper circuits must remain enabled. When disabled,
the squelch startup sequence is synchronous in nature and the squelch indication signal
sent out of Modphy is stable/filtered.
24
1h
RW
i_rxsquelchstby_h:
Fast Squelch Enable Mode Bit to keep the IREF (ivrefen) on
during P2 and reduce squelch startup time.