Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2144
Datasheet
Default: 00000000h
18.6.33
Message Signaled Interrupt Message Data (MSI_MD)—Offset
8Ch
Access Method
Default: 0000h
18.6.34
High Speed Configuration 1 (HSCFG1)—Offset A0h
Not for EDS
Access Method
Default: 00000100h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Up
pe
rA
d
d
r
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
Upper Addr (UpperAddr):
Upper DW of system specified message address.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 16 bits)
Offset:
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
0000h
RW
Data:
This 16-bit field is programmed by system software if MSI is enabled. Its content
is driven onto the lower word (PCI AD(15:0)) during the data phase of the MSI memory
write transaction. The Multiple Message Enable field (bits 6-4 of the Message Control
register) defines the number of low order message data bits the function is permitted to
modify to generate its system software allocated vectors. For example, a Multiple
Message Enable encoding of 010 indicates the function has been allocated four vectors
and is permitted to modify message data bits 1 and 0 (a function modifies the lower
message data bits to generate the allocated number of vectors). If the Multiple Message
Enable field is 000, the function is not permitted to modify the message data.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: