Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2155
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
SP
ARE
US
H_
DEV
ID
XDD_E
N
SRA
M
PW
RG
TDIS
US
B
2
PL
LS
DI
S
US
BIO
PMDIS
XH
CD
CG
DI
S
US
BRDIS
SS
PR
TC
N
T
HS
PR
TC
NT
XH
CFD
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
23:14
000h
RO/V
Spare Fuses (SPARE):
Will be used for VLV2.
Power Well:
SUS
13:11
000b
RO/V
USH DevID (USH_DEVID):
LSB bits of USH PCIe Device ID The 3 LSB bits enable
defining up to 8 separate USH SKUs if required
Power Well:
SUS
10
0b
RO/V
Debug Device Enable (XDD_EN):
0 : Debug Device is Enabled 1: Debug Device is
Disabled
Power Well:
SUS
9
0h
RO/V
SRAM Power Gating Disable (SRAMPWRGTDIS):
0: SRAM Power Gating Enabled 1:
SRAM Power Gating Disabled
Power Well:
SUS
8
0h
RO/V
USB2 PLL Shutdown Disable (USB2PLLSDIS):
0: USB2 PLL shutdown enabled 1:
USB2 PLL shutdown disabled
Power Well:
SUS
7
0h
RO/V
USB I/O Power Management Disable (USBIOPMDIS):
0: USB2 HW LPM and USB3
HW Ux under XHC enabled 1: USB2 HW LPM and USB3 HW Ux under XHC disabled
Power Well:
SUS
6
0h
RO/V
XHC Dynamic Clock Gating Disable (XHCDCGDIS):
0: USB3 (XHC) dynamic clock
gating enabled 1: USB3 (XHC) dynamic clock gating disabled
Power Well:
SUS
5
0h
RO/V
USBr Disable (USBRDIS):
0: USBr enabled 1: USBr disabled
Power Well:
SUS
4:3
0h
RO/V
SS Port Count (SSPRTCNT):
This field specifies number of SS ports present.
Supported combinations are: 00: 6 SS ports 01: 4 SS ports 10: 2 SS ports 11: 0 SS
ports
Power Well:
SUS
2:1
0h
RO/V
HS Port Count (HSPRTCNT):
This field specifies number HS ports present. Supported
combinations are: 00: 14 HS ports 01: 12 HS ports 10: 10 HS ports 11: N/A (reserved)
Power Well:
SUS