Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

2169

8150–8153h

4

“Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—Offset

8150h” on page 2310

00000000h

8154–8157h

4

“AUX Power Management Control (AUX_CTRL_REG2)—Offset 8154h”

01390206h

8164–8167h

4

“USB2 PHY Power Management Control (USB2_PHY_PMC)—Offset

8164h” on page 2314

000000FCh

8168–816Bh

4

“USB Power Gating Control (USB_PGC)—Offset 8168h” on page 2315

00000000h

816C–816Fh

4

“xHCI Aux Clock Control Register (XHCI_AUX_CCR)—Offset 816Ch” on

00000400h

8170–8173h

4

“USB LPM Parameters (USB_LPM_PARAM)—Offset 8170h” on

00090032h

8174–8177h

4

“xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)—Offset

8174h” on page 2319

0040047Dh

8178–817Bh

4

“xHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)—Offset

8178h” on page 2321

000017FFh

817C–817Fh

4

“xHC Latency Tolerance Parameters - High Idle Time Control

(XLTP_HITC)—Offset 817Ch” on page 2321

00000000h

8180–8183h

4

“xHC Latency Tolerance Parameters - Medium Idle Time Control

(XLTP_MITC)—Offset 8180h” on page 2322

00000000h

8184–8187h

4

“xHC Latency Tolerance Parameters Low Idle Time Control

(XLTP_LITC)—Offset 8184h” on page 2323

00000000h

8344–8347h

4

“USB EP Type Lock Policy (USB_EP_TLP)—Offset 8344h” on page 2324

00000000h

8348–834Bh

4

“USB EP Type Lock Policy - Port Control 1 (USB_EP_TLP1)—Offset

8348h” on page 2327

00000000h

834C–834Fh

4

“USB EP Type Lock Policy - Port Control 2 (USB_EP_TLP2)—Offset

834Ch” on page 2329

00000000h

8460–8463h

4

“USB Legacy Support Capability (USBLEGSUP)—Offset 8460h” on

00000801h

8464–8467h

4

“USB Legacy Support Control Status (USBLEGCTLSTS)—Offset 8464h”

00000000h

8480–8483h

4

“Debug Capability ID Register (DCID)—Offset 8480h” on page 2332

0005000Ah

8484–8487h

4

“Debug Capability Doorbell Register (DCDB)—Offset 8484h” on

00000000h

8488–848Bh

4

“Debug Capability Event Ring Segment Table Size Register

(DCERSTSZ)—Offset 8488h” on page 2334

00000000h

8490–8497h

8

“Debug Capability Event Ring Segment Table Base Address Register

(DCERSTBA)—Offset 8490h” on page 2335

0000000000000000h

8498–849Fh

8

“Debug Capability Event Ring Dequeue Pointer Register (DCERDP)—

Offset 8498h” on page 2335

0000000000000000h

84A0–84A3h

4

“Debug Capability Control Register (DCCTRL)—Offset 84A0h” on

00000000h

84A4–84A7h

4

“Debug Capability Status Register (DCST)—Offset 84A4h” on

00000000h

84A8–84ABh

4

“Debug Capability Port Status and Control Register (DCPORTSC)—

Offset 84A8h” on page 2338

00000000h

84B0–84B7h

8

“Debug Capability Context Pointer Register (DCCP)—Offset 84B0h” on

0000000000000000h

Table 211.

Summary of USB xHCI Memory Mapped I/O Registers—MBAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value