Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2171
Default: 0100h
18.7.3
Structural Parameters 1 (HCSPARAMS1)—Offset 4h
This register defines basic structural parameters supported by this xHC
implementation: Number of Device Slots support, Interrupters, Root Hub ports, etc.
This register is modified and maintained by BIOS.
Access Method
Default: 07000820h
15
12
8
4
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
HC
IVE
R
S
ION
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
0100h
RO
Host Controller Interface Version Number (HCIVERSION):
This is a two-byte field
containing a BCD encoding of the xHCI specification revision number supported by this
host controller. The most significant byte of this field represents a major revision, and
the least significant bit is the minor revision, e.g. 0100h corresponds to xHCI version
1.0.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
MaxP
or
ts
Rsvd1
Ma
xI
n
tr
s
MaxSlots
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
07h
RO
Number of Ports (MaxPorts):
This field specifies the maximum Port Number value,
i.e the highest number of Port Register Sets that are addressable in the Operational
Register Space (refer to the xHCI for USB specification). Valid values are in the range of
1h to FFh.
The value in this field shall reflect the maximum Port Number value assigned by an xHCI
Supported Protocol Capability
, described in the xHCI for USB specification. Software
shall refer to these capabilities to identify whether a specific Port Number is valid, and
the protocol supported by the associated Port Register Set.
Power Well:
Core
23:19
00h
RW/L
Rsvd1:
Reserved.
Power Well:
Core