Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2175

8

1b

RW/L

This flag indicates whether the host controller 

implementation parses all Event Data TRBs while advancing to the next TD after a Short 

Packet, or skips all but the first Event Data TRB. A 1 in this bit indicates that all Event 

Data TRBs are parsed. A 0 in this bit indicates that only the first Event Data TRB is 

parsed. Refer to the xHCI for USB specification.

Core

7

1b

RW/L

This flag indicates whether the host controller 

implementation supports Secondary Stream IDs. A 1 in this bit indicates that Secondary 

Stream ID decoding is not supported. A 0 in this bit indicates that Secondary Stream ID 

decoding is supported. Refer to the xHCI for USB specification.

Core

6

1b

RW/L

This flag indicates whether the host 

controller implementation supports Latency Tolerance Messaging (LTM). A 1 in this bit 

indicates that LTM is supported. A 0 in this bit indicates that LTM is not supported. Refer 

to the xHCI for USB specification.

Core

5

1b

RW/L

This flag indicates whether the host controller 

implementation supports a Light Host Controller Reset. A 1 in this bit indicates that Light 

Host Controller Reset is supported. A 0 in this bit indicates that Light Host Controller 

Reset is not supported. The value of this flag affects the functionality of the Light Host 

 (LHCRST) flag in the USBCMD register. Refer to the xHCI for USB 

specification.

Core

4

0b

RW/L

This bit indicates whether the xHC root hub ports support 

port indicator control. When this bit is a 1, the port status and control registers include a 

read/ writeable field for controlling the state of the port indicator. Refer to the xHCI for 

USB specification for the definition of the Port Indicator Control field.

Core

3

0b

RO

This flag indicates whether the host controller 

implementation includes port power control. A 1 in this bit indicates the ports have port 

power switches. A 0 in this bit indicates the port does not have port power switches. The 

value of this flag affects the functionality of the PP flag in each port status and control 

register. See the xHCI for USB specification.

Core

2

0b

RW/L

If this bit is set to 1, then the xHC uses 64 byte Context data 

structures. If this bit is cleared to 0, then the xHC uses 32 byte Context data structures. 

Note: This flag does not apply to Stream Contexts.

Core

1

0b

RW/L

This flag identifies whether the xHC has 

implemented the Bandwidth Negotiation. Values for this flag have the following 

interpretation: 
•

0 = BW Negotiation not implemented 

•

1 = BW Negotiation implemented 

Refer to the xHCI for USB specification for more information on Bandwidth Negotiation.

Core