Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2182

Datasheet

Default: 00000001h

This register is used by software to enable or disable the reporting of the reception of 

specific USB Device Notification Transaction Packets. A Notification Enable (Nx, where x 

= 0 to 15) flag is defined for each of the 16 possible device notification types. If a flag 

is set for a specific notification type, a Device Notification Event shall be generated 

when the respective notification packet is received. After reset, all notifications are 

disabled. Refer to specification eXtensible Host Controller Interface for Universal Serial 

Bus (xHCI). This register shall be written as a Dword. Byte writes produce undefined 

results.

Default: 00000000h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Rsvd

1

PA

G

E

S

IZ

E

31:16

0000h

RO

Reserved.

Core

15:0

0001h

RO

This field defines the page size supported by the xHC 

implementation. This xHC supports a page size of 2^(n+12) if bit n is Set. For example, 

if bit 0 is Set, the xHC supports 4k byte page sizes.  

For a Virtual Function, this register reflects the page size selected in the System Page 

 field of the SR-IOV Extended Capability structure. For the Physical Function 0, this 

register reflects the implementation dependent default xHC page size.   

Various xHC resources reference PAGESIZE to describe their minimum alignment 

requirements. The maximum possible page size is 128M.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Rsvd

1

N0_N15

31:16

0000h

RO

Reserved.

Core