Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2184

Datasheet

The Command Ring Control Register provides Command Ring control and status 

capabilities, and identifies the address and Cycle bit state of the Command Ring 

Dequeue Pointer.

Default: 00000000h

2

0b

RW/S

Writing a '1' to this bit shall immediately terminate the 

currently executing command, stop the Command Ring, and generate a Command 

Completion Event with the Completion Code set to Command Ring Stopped. Refer to the 

xHCI for USB specification for more information on aborting a command.  

The next write to the Host Controller Doorbell with DB Reason field set to Host 

 shall restart the Command Ring operation.  

Writes to this flag are ignored by the xHC if Command Ring Running (CCR) = '0'.  

Reading this bit always returns '0'.

Core

1

0b

RW/S

Writing a '1' to this bit shall stop the operation of the Command 

Ring after the completion of the currently executing command, and generate a 

 with the Completion Code set to Command Ring Stopped 

and the Command TRB Pointer set to the current value of the Command Ring Dequeue 

Pointer. Refer to the xHCI for USB specification for more information on stopping a 

command.  

The next write to the Host Controller Doorbell with DB Reason field set to Host 

 shall restart the Command Ring operation.  

Writes to this flag are ignored by the xHC if Command Ring Running (CCR) = '0'.  

Reading this bit shall always return '0'.

Core

0

0b

RW

This bit identifies the value of the xHC Consumer Cycle State 

(CCS) flag for the TRB referenced by the Command Ring Pointer. Refer to the xHCI for 

USB specification for more information.  

Writes to this flag are ignored if Command Ring Running is '1'.  

If the CRCR is written while the Command Ring is stopped (CCR = '0'), then the value of 

this flag shall be used to fetch the first Command TRB the next time the Host Controller 

 register is written with the DB Reason field set to Host Controller Command.  

If the CRCR is not written while the Command Ring is stopped (CRR = '0'), then the 

Command Ring shall begin fetching Command TRBs using the current value of the 

Internal Command Ring CCS flag.  

Reading this flag always returns '0'.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRP