Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2279
18.7.145 Override EP Flow Control (HOST_CLR_MASK_REG)—Offset
8078h
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0
HO
S
T
_C
TRL
_
C
A
P
_
REG
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0000FCC0h
RW/L
Host Controller Capability (HOST_CTRL_CAP_REG):
This is a register that describe
the host controller the extended cap location. It includes the
XECP_HOST_NEXT_CAP_OFFSET and VEND_DEF_HOST_CAP_ID_192
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
SVD
SN
DC
EP
_NUM
CI
S
M
Bit
Range
Default &
Access
Field Name (ID): Description
31:10
000000h
RO
RESERVED (RSVD):
Reserved.
Power Well:
Core
9:5
00h
RW
Slot Number Default Config (SNDC):
5bits of slot number as a default configuration.
It can scale to max of 128 slots.
Power Well:
Core
4:1
0h
RW
EP Number (EP_NUM):
4bits of EP number
Power Well:
Core
0
0b
RW
Clear Internal Scheduler's Mask (CISM):
This is a register that is used to clear the
internal scheduler's mask that is used to stop scheduling a particular EP. Bit0 indicates
the direction of the EP
Power Well:
Core