Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2280
Datasheet
18.7.146 Clear Active IN EP ID Control
(HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch
Access Method
Default: 00000000h
18.7.147 Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset
8080h
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HOST_CLR_IN_
E
P_V
ALID_REG
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG):
This register is
used to clear the internal valid IN EP array that TRM stored in order to guarantee one IN
EP per port. This register allows software to clear the valid bit of each port IN EP. This
field indicates the port number. For a 2port configuration, only bit1:0 are valid. It can
scale for the max number of ports that we support.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
SNDC
EP
_
N
UM
CIS
PM