Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2289
18.7.155 Scheduler Async Delay
(HOST_CTRL_SCH_ASYNC_DELAY_REG)—Offset 80D4h
Global defaults for inserting delays between packets in the scheduler for async. types.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
RSVD
PT
T
P_O
VR
H
_
SB
W
P
P_O
VR
H
_
SB
W
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
RO
RESERVED (RSVD):
Reserved.
Power Well:
Core
23:12
032h
RW
Per TT Packet Overhead System BW (PTTP_OVRH_SBW):
BW calculation:
Overhead per TT packet for System BW calculations. see white paper.
Power Well:
Core
11:0
010h
RW
Per Packet Overhead System BW (PP_OVRH_SBW):
BW calculation: Overhead per
packet for System BW calculations. see white paper.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD
HS
_BD_EN
H
S
_
B
D_
DE
F
FS
_BD_EN
FS
_
B
D_
DE
F
HS
_CD
_
E
N
H
S
_
C
D_
DE
F
FS_CD_EN
FS
_
C
D_
DE
F
LS_CD_EN
LS
_
C
D_
DE
F
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
000h
RO
RESERVED (RSVD):
Reserved.
Power Well:
Core
19
0b
RW
High-Speed Bulk Delay Enable (HS_BD_EN):
Reserved.
Power Well:
Core