Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2291
18.7.157 AUX Power Management Control (AUX_CTRL_REG1)—Offset
80E0h
Access Method
Default: 808DBCA0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:4
0000000h
RO
RESERVED (RSVD):
Reserved.
Power Well:
Core
3:0
0h
WO
Allow Software USB PHY RST (ALL_SW_UP_RST):
Allow a USB PHY reset being
issued by software. Writing to this register with bit set to 1 will reset the USB PHY that is
connected to the port. Bit3:0 indicates the port number of the USB PHY
Power Well:
SUS
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 0 0 0 0 0
D3_HO
T
_FXN_EN
ALL_L1_CORE
_
CG
AL
_E
P_S
E
X
T
ALL_E
P_
R
CP
AL_P
E
R
ST_FRST
OVR_PC
IE
_P
2_P1
S
E
T
_
ISSV
_1
CL
R
_
ISSV
_0
EN_SRE
_SW_LD
RS
VD_1
FO
RC
E
_
SR1
CPTR
CID
S
1
CID
S
0
EN_CFG_U
P2
CC
G
D
EN_C
FG_RDP3
EN_CFG_P
IPE_RST
EN_FIL
T_TX_IDL
E
EN
_
H
E
_
GE
N_
PM
E
EN_IS
O
L
EN_L1_P
2_OVR
EN_C
ORE
_
CG
E
N
_P
HY_ST
S
_T
O
IG
N_APE_P
C
EN_P2_OVR_P1
E
N
_P
2_RE
M
_W
AK
E
FORCED_PM_ST
A
T
E
INIT_FPMS
Bit
Range
Default &
Access
Field Name (ID): Description
31
1b
RW
D3 Hot function enable register (D3_HOT_FXN_EN):
This bit is from a pin input
set to 1, but we allow software to alter it, if needed.
•
•
1 = D3 hot enabled
•
0 = D3 hot not abled.
Power Well:
SUS
30
0b
RW
Allow L1 Core Clock Gating (ALL_L1_CORE_CG):
When set to 1 allows core clock
being gated during L1 state.
Power Well:
SUS
29
0b
RW
Allow Engine PHY Status Extension (AL_EP_SEXT):
When set to 1 allows the
engine to extend PHY status of PCIe PIPE for one more cycle. This is due to the fact that
our rate change function has a potential of not being able to sample the phystatus
signal.
Power Well:
SUS
28
0b
RW
Allow Engine PCIe Rate Change Passing (ALL_EP_RCP):
When set to 1 allows the
engine to pass PCIe rate change signal as it is from PCIe core to PCIe PHY.
Power Well:
SUS