Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2290
Datasheet
18.7.156 AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 80D8h
Access Method
Default: 00000000h
18:16
0h
RW
High-Speed Bulk Delay Default (HS_BD_DEF):
(0=125us,1=250us,2=500us,3=1ms,...)
Power Well:
Core
15
0b
RW
Full-Speed Bulk Delay Enable (FS_BD_EN):
Reserved.
Power Well:
Core
14:12
0h
RW
Full-Speed Bulk Delay Default (FS_BD_DEF):
(0=125us,1=250us,2=500us,3=1ms,...)
Power Well:
Core
11
0b
RW
High-Speed Control Delay Enable (HS_CD_EN):
Reserved.
Power Well:
Core
10:8
0h
RW
High-Speed Control Delay Default (HS_CD_DEF):
(0=125us,1=250us,2=500us,3=1ms,...)
Power Well:
Core
7
0b
RW
Full-Speed Control Delay Enable (FS_CD_EN):
Reserved.
Power Well:
Core
6:4
0h
RW
Full-Speed Control Default (FS_CD_DEF):
(0=125us,1=250us,2=500us,3=1ms,...)
Power Well:
Core
3
0b
RW
Low-Speed Control Delay Enable (LS_CD_EN):
Reserved.
Power Well:
Core
2:0
0h
RW
Low-Speed Control Delay Default (LS_CD_DEF):
(0=125us,1=250us,2=500us,3=1ms,...)
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
ALL_S
W
_
U
P_RST