Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2292
Datasheet
27
0b
RW
Allow Engine PERST Fundamental Reset (AL_PERST_FRST):
When set to 1 allow
engine to treat PERST# as a foundamental reset
Power Well:
SUS
26
0b
RW
Overwrite PCIe P2 to P1 (OVR_PCIE_P2_P1):
When set to 1 will overwrite a PCIe
powerdown state of P2 to P1.
Power Well:
SUS
25
0b
RW
Set Internal SSV 1 (SET_ISSV_1):
When set to 1 set the internal SSV to 1.
Power Well:
SUS
24
0b
RW
Clear Internal SSV 0 (CLR_ISSV_0):
When set to 1 clear the internal SSV to 0.
Power Well:
SUS
23
1b
RW
Enable save_restore_enable SW Loading (EN_SRE_SW_LD):
This is a bit that
enables the save_restore_enable signal being loaded when a software command has set
Save bit. This is a debug function.
Power Well:
SUS
22
0b
RW
RESERVED (RSVD_1):
Reserved.
Power Well:
SUS
21
0b
RW
Force save_restore 1 (FORCE_SR1):
When set to 1, it will force the save_restore
flag to 1. This flag is an bit to ensure that we have masked the update during low power
state. If software write this bit to 1, it must write it to 0 in order to resume the normal
save and restore function.
Power Well:
SUS
20
0b
RW
cfg pcie txreg rd (CPTR):
Reserved.
Power Well:
SUS
19
1b
RW
cfg iob drivestrength[1] (CIDS1):
Reserved.
Power Well:
SUS
18
1b
RW
cfg iob drivestrength[0] (CIDS0):
Reserved.
Power Well:
SUS
17
0b
RW
Enable CFG USB P2 (EN_CFG_UP2):
When set to '1' enable cfg usb p2
Power Well:
SUS
16
1b
RW
cfg clk gate dis (CCGD):
Reserved.
Power Well:
SUS
15
1b
RW
Enable CFG RXDET P3 (EN_CFG_RDP3):
When set to '1' enable cfg rxdet p3
Power Well:
SUS
14
0b
RW
Enable CFG PIPE Reset (EN_CFG_PIPE_RST):
When set to '1' enable cfg pipe rst
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description