Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2295
Default: 00800080h
18.7.160 SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—
Offset 80ECh
Access Method
Default: 18010600h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RBUF_WM
XBUF_WM
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0080h
RW
RBUF water mark (RBUF_WM):
Reserved.
Power Well:
Core
15:0
0080h
RW
XBUF water mark (XBUF_WM):
Reserved.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
FO
RC
E
_
LT
S
S
M_ST
D
L_L
TS
SM_ST
DL_U0
FORCED
_
C
MP_P
A
T
EN_LE
S
_CN
T
DEB
U
G_MD_SE
L
PH
Y
_
LP_LA
T
LR_MIN_TM
LP_MIN_TM
FORCE_LA
_
PMC
DL_REC_U0
LINK_F
TM
DIS_LINK
_S
C
R
AM
DL
_
U
3_U0
DL
_
U
2_U0
DL
_
U
1_U0
EN_LINK_LB_MAST
DIS_LINK_C
M
Bit
Range
Default &
Access
Field Name (ID): Description
31:27
03h
RW
Force LTSSM State (FORCE_LTSSM_ST):
LTSSM state to be forced This value is for
test purpose only.
Power Well:
Core
26
0b
RW
Direct Link LTSSM State (DL_LTSSM_ST):
•
•
0 = Normal operation mode
•
1 = Direct link to a specific state specified by bit 31:27
This bit is for test purposes only. It shall be written 0 in normal operation mode.
Power Well:
Core