Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2314
Datasheet
18.7.176 USB2 PHY Power Management Control (USB2_PHY_PMC)—
Offset 8164h
Access Method
Default: 000000FCh
0
0b
RW
Enable P2 Overwrite P1 Allowed Detect (EN_P2OVRP1_ADET):
When set to 1,
enables a function that can detect whether or not enable P2 overwrite P1 function. The
condition to get to P2 overwrite is when engine is in idle conditions. This means that
there is no ISO EP pending.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0
RSVD
E
N
_CMDM_TXRX
B
EN_T
T
E
_TXRX
B
EN_
ID
M
A
_
T
X
R
X
B
EN_O
DMA_TXRX
B
EN_TRM_TXRX
B
E
N
_SC
H
_TXRX
B
EN_
R
X
B
_
C
D
EN_T
XB_C
D
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
000000h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
7
1b
RW
EN_CMDM_TXRXB:
Enable Command Manager Active indication for Tx/Rx Bias circuit
HS Phy PM Policy
Power Well:
Core
6
1b
RW
EN_TTE_TXRXB:
Enable TTE Active indication for Tx/Rx Bias circuit HS Phy PM Policy
Power Well:
Core
5
1b
RW
EN_IDMA_TXRXB:
Enable IDMA Active indication for Tx/Rx Bias circuit HS Phy PM
Policy
Power Well:
Core
4
1b
RW
EN_ODMA_TXRXB:
Enable ODMA Active indication for Tx/Rx Bias circuit HS Phy PM
Policy
Power Well:
Core
3
1b
RW
EN_TRM_TXRXB:
Enable Transfer Manager Active indication for Tx/Rx Bias circuit HS
Phy PM Policy
Power Well:
Core