Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2316
Datasheet
Default: 00000400h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
RS
VD
PA
RUSB3_E
NG
_GEN
PA
RUSB3_LINK_GEN
PA
RUSB2_CLK_GEN
U
S
H
IP_PC
GE
N
RS
VD1
USB3_
A
C
_
CGE
RX_D
T
_
A
C
G
U2R_BM_C
G
FT
C
G
PU
2
E
USB2_PC_TE
XH
CI_AC_GE
XHCI_
A
PM
B_CGE
U
S
B3_AC_T
G
E
US
B3
_AP
_
CGE
MPP_
AC_
G
EU
2
MPP
_
AC
_GE_DD
U
3
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
000h
RO
Reserved (RSVD):
Reserved.
19
0b
RW
USB3 Partition Engine/Link trunk gating Enable (PARUSB3_ENG_GEN):
When
set to 1 enables gating of the SOSC trunk to the XHCI engine and link in the PARUSB3
partition.
Power Well:
SUS
18
0b
RW
USB3 Partition Frame Timer trunk gating Enable (PARUSB3_LINK_GEN):
When
set to 1 enables gating of the SOSC trunk to the Frame timer in the PARUSB3 partition.
Power Well:
SUS
17
0b
RW
USB2 link partition clock gating enable (PARUSB2_CLK_GEN):
When set to 1
enables gating of the SOSC trunk to the USB2 link and Phy logic in the PARUSB2
partition.
Power Well:
SUS
16
0b
RW
USB2/USHIP 12.5 MHz partition clock gating enable (USHIP_PCGEN):
When set
to 1 enables gating of the 12.5 MHz SOSC trunk to the USB2 and USHIP logic in the
PARUSB2 partition.
Power Well:
SUS
15
0b
RO
Reserved1 (RSVD1):
Reserved
14
0b
RW
USB3 Port Aux/Core clock gating enable (USB3_AC_CGE):
When set, allows the
aux_cclk clock into the USB3 port to be gated when conditions are met. Usage of this bit
is further qualified with xHC Dynamic Clock Gating Disable fuse. If the fuse disables
dynamic clock gating, Aux clock gating will not be enabled either. This bit always returns
the value that was written to it, irrespective of the setting of xHC Dynamic Clock Gating
Disable fuse.
Power Well:
SUS