Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2342
Datasheet
18.7.200 Debug Capability Device Descriptor Info Register 2 (DCDDI2)—
Offset 84BCh
Access Method
Default: 00000000h
18.7.201 Debug Capability Descriptor Parameters (DCDP)—Offset 8530h
The Debug Capability Device Descriptor Register 2 identifies the Device Revision and
Product ID values that shall be reported by DbC in its Device Descriptor when it is
enumerated by a Debug Host. Refer to section 9.6.1, Table 9-8 in the Universal Serial
Bus 3.0 Specification.
Access Method
Default: 00000000h
7:0
00h
RW
DbC Protocol (DBCPR):
This field is presented by the Debug Device in the USB
Interface Descriptor bInterfaceProtocol field.
•
•
0 = Debug Target vendor defined
•
1 = GNU Remote Debug Command Set supported
•
2-255 = Reserved
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DREV
PI
D
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RW
Device Revision (DREV):
This field is presented by the Debug Device in the USB
Device Descriptor bcdDevice field.
Power Well:
Core
15:0
0000h
RW
Product ID (PID):
This field is presented by the Debug Device in the USB Device
Descriptor idProduct field.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h