Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2370
Datasheet
18.9.1
Capability Registers Length and HC Interface Version
Number (CAP_HCIV)—Offset 0h
Access Method
Default: 01000020h
A4–A4h
1
00000000h
A8–AFh
8
0000000000000000
h
h
B0–B3h
4
00007F01h
Table 213. Summary of USB EHCI Memory Mapped I/O Registers—MBAR (Continued)
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default Value
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
HC
IVER
SIO
N
_B
0_
0
RSVD
CA
PLENGTH_0
Bit
Range
Default
& Access
Field Name (ID): Description
31:16
0100h
RO
Host Controller Interface Version Number (HCIVERSION_B0_0): This
is a two-byte register containing a BCD encoding of the version number of
interface that this host controller interface conforms.
is a two-byte register containing a BCD encoding of the version number of
interface that this host controller interface conforms.
Power Well: Core
15:8
00h
RO
Reserved (RSVD): Reserved.
7:0
20h
RO
Capability Registers Length (CAPLENGTH_0): This register is used as an
offset to add to the Memory Base Register to find the beginning of the
Operational Register Space. This is fixed at 20h, indicating that the Operation
Registers begin at offset 20h.
offset to add to the Memory Base Register to find the beginning of the
Operational Register Space. This is fixed at 20h, indicating that the Operation
Registers begin at offset 20h.
Power Well: Resume