Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2371
18.9.2
Host Controller Structural Parameters (HCSPARAMS)—
Offset 4h
Access Method
Default: 00200008h
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 32 bits)
MBAR Reference: 
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
RSVD
DP
_N_
0
RSVD
RSVD
N_CC_
0
N_PCC_
0
PRR_
0
RSVD
RSVD
NPO
R
T
S
_
0
Bit 
Range
Default 
& Access
Field Name (ID): Description
31:24
00h
RO
Reserved (RSVD): Reserved.
23:20
2h
RO
Debug Port Number (DP_N_0): Hardwired to 2h, indicating that the 
Debug Port is on the 2nd port on the EHC. This register is only reset by the 
resume power well going low. It is not reset by a D3-to-D0 state transition or 
HCRESET (Host Controller Reset)
Power Well: Resume
19:17
000b
RO
Reserved (RSVD): Reserved.
16
0b
RO
Reserved (RSVD): Reserved.
15:12
0h
RO
Number of Companion Controllers (N_CC_0): This field indicates the 
number of companion controllers associated with this USB 2.0 host 
controller. A zero in this field indicates there are no companion host 
controllers. Port-ownership hand-off is not supported. Only high-speed 
devices are supported on the host controller root ports. A value larger than 
one in this field indicates there are companion USB 1.1 host controller(s). 
Port-ownership hand-offs are supported. High, Full- and Low-speed devices 
are supported on the host controller root ports. There are no companion 
controllers. This field is set to '0' as Read-Only bit.
Power Well: Core