Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2373
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1
RSVD
AS
PF
C
_
0
PS
PF
C_0
EECP
_
0
IS
T_0
RSVD
AS
P
C
_0
PF
LF
_0
AC64_
0
Bit
Range
Default
& Access
Field Name (ID): Description
31:18
000000000
00000b
RO
Reserved (RSVD): Reserved.
17
1b
RW
Asynchronous Schedule Prefetch Capability (ASPFC_0): This bit
indicates that tthe hardware support the Asynch schedule prefetch enable bit
in the USB command register.
indicates that tthe hardware support the Asynch schedule prefetch enable bit
in the USB command register.
Power Well: Resume
16
1b
RW
Periodic Schedule Prefetch Capability (PSPFC_0): This bit indicates that
the EHC hardware supports the Periodic Schedule prefetch bit in the USB2
Command Register.
the EHC hardware supports the Periodic Schedule prefetch bit in the USB2
Command Register.
Power Well: Core
15:8
68h
RO
EHCI Extended Capabilities Pointer (EECP_0): This field is hardwired to
68h, indicating that the EHCI capabilities list exists and begins at offset 68h
in the PCI configuration space.
68h, indicating that the EHCI capabilities list exists and begins at offset 68h
in the PCI configuration space.
Power Well: Resume
7:4
8h
RO
Isochronous Scheduling Threshold (IST_0): This field indicates, relative
to the current position of the executing host controller, where software can
reliably update the isochronous schedule. When bit [7] is zero, the value of
the least significant 3 bits indicates the number of micro-frames a host
controller hold a set of isochronous data structures (one or more) before
flushing the state. When bit [7] is a one, then host software assumes the
host controller may cache an isochronous data structure for an entire frame.
Refer to the EHCI specification for details on how software uses this
information for scheduling isochronous transfers. The Intel USB2 hardwires
this field to 8h.
to the current position of the executing host controller, where software can
reliably update the isochronous schedule. When bit [7] is zero, the value of
the least significant 3 bits indicates the number of micro-frames a host
controller hold a set of isochronous data structures (one or more) before
flushing the state. When bit [7] is a one, then host software assumes the
host controller may cache an isochronous data structure for an entire frame.
Refer to the EHCI specification for details on how software uses this
information for scheduling isochronous transfers. The Intel USB2 hardwires
this field to 8h.
Power Well: Resume
3
0b
RO
Reserved (RSVD): Reserved.
2
0b
RO
Asynchronous Schedule Park Capability (ASPC_0): This bit is hardwired
to 0 indicating that the Host Controller does not support this optional feature.
to 0 indicating that the Host Controller does not support this optional feature.
Power Well: Resume