Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2421
16
0b
RWC
DONE_STS (DONESTS_0): Read/Write-Clear. This bit is set by hardware to
indicate that the request is complete. Writing a 1 to this bit will clear it if it is
set. Writing a 0 to this bit has no effect. Reset default = 0
indicate that the request is complete. Writing a 1 to this bit will clear it if it is
set. Writing a 0 to this bit has no effect. Reset default = 0
Power Well: Core
15:12
0000b
RO
LINK_ID_STS (LINKIDSTS_0): Read-Only. This field identifies the link
interface. It is hardwired to 0h to indicate that it is a USB Debug Port.
interface. It is hardwired to 0h to indicate that it is a USB Debug Port.
Power Well: Core
11
0b
RO
Reserved (RSVD): Reserved.
10
0b
RO
IN_USE_CNT (INUSECNT_0): Set by software to indicate that the port is
in use. Cleared by software to indicate that the port is free and may be used
by other software. This bit is cleared after reset. (This bit has no affect on
hardware.)
in use. Cleared by software to indicate that the port is free and may be used
by other software. This bit is cleared after reset. (This bit has no affect on
hardware.)
Power Well: Core
9:7
000b
RO
EXCEPTION_STS (EXCP_STS_0): Read-Only. This field indicates the
exception when the ERROR_GOOD#_STS bit is set. This field should be
ignored if the ERROR_GOOD#_STS bit is 0. 000 No Error. Note: this should
not be seen, since this field should only be checked if there is an erro. 001
Transaction error: indicates the USB2 transaction had an error (CRC, bad
PID, timeout, etc.) 010 HW error. Request was attempted (or in progress)
when port was suspended or reset. All Others are reserved Reset default =
000b
exception when the ERROR_GOOD#_STS bit is set. This field should be
ignored if the ERROR_GOOD#_STS bit is 0. 000 No Error. Note: this should
not be seen, since this field should only be checked if there is an erro. 001
Transaction error: indicates the USB2 transaction had an error (CRC, bad
PID, timeout, etc.) 010 HW error. Request was attempted (or in progress)
when port was suspended or reset. All Others are reserved Reset default =
000b
Power Well: Core
6
0b
RO
ERROR_GOOD_STS (ERRGOODSTS_0): Read-Only. The hardware clears
this bit to 0 upon the proper completion of a read or write. The hardware sets
this bit to indicate that an error has occurred. Details on the nature of the
error are provided in the Exception field. Reset default = 0.
this bit to 0 upon the proper completion of a read or write. The hardware sets
this bit to indicate that an error has occurred. Details on the nature of the
error are provided in the Exception field. Reset default = 0.
Power Well: Core
5
0b
RW
GO_CNT (GOCNT_0): Software sets this bit to cause the hardware to
perform a read or write request. Writing a 0 to this bit has no effect. Writing
a 1 to this bit when it is already set may result in undefined behavior. When
set, the hardware clears this bit when the hardware sets the DONE_STS bit.
Reset default = 0.
perform a read or write request. Writing a 0 to this bit has no effect. Writing
a 1 to this bit when it is already set may result in undefined behavior. When
set, the hardware clears this bit when the hardware sets the DONE_STS bit.
Reset default = 0.
Power Well: Core
4
0b
RW
WRITE_READ_CNT (WRRDCNT_0): Software sets this bit to indicate that
the current request is a write. Software clears this bit to indicate that the
current request is a read. Reset default = 0.
the current request is a write. Software clears this bit to indicate that the
current request is a read. Reset default = 0.
Power Well: Core
Bit
Range
Default
& Access
Field Name (ID): Description