Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2519
19.6.61
GTXTHRCFG—Offset C108h
Global Tx Threshold Control Register
Access Method
Default: 230A0000h
19.6.62
GRXTHRCFG—Offset C10Ch
Global Rx Threshold Control Register
Access Method
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GTXTH
R
CFG_RS
V
D
4
US
BXMITPKT
CNTE
N
GTXTH
R
CFG_RS
V
D
3
US
B
X
M
ITP
KT
CN
T
U
S
BMAXTX
BU
RS
T
S
IZE
GTXTH
R
CFG_RS
V
D
2
GTXTH
R
CFG_RS
V
D
1
Bit
Range
Default &
Access
Description
31:30
0h
RW
GTXTHRCFG_RSVD4:
Reserved
29
1h
RW
USBXMITPKTCNTEN:
USB Transmit Packet Count Enable (USBTxPktCntSel). This field
enables/disables the USB transmission multi-packet thresholding: 0: USB transmission
multi-packet thresholding is disabled, the core can only start transmission on the USB
after the entire packet has been fetched into the corresponding TXFIFO. 1: USB
transmission multi-packet thresholding is enabled. The core can only start transmission
on the USB after USB Transmit Packet Count amount of packets for the USB transaction
(burst) are already in the corresponding TXFIFO This mode is only valid in the host
mode. It is only used for SuperSpeed.
28
0h
RO
GTXTHRCFG_RSVD3:
Reserved
27:24
3h
RO
USBXMITPKTCNT:
USB Transmit Packet Count (USBTxPktCnt) This field specifies the
number of packets that must be in the TXFIFO before the core can start transmission for
the corresponding USB transaction (burst). This field is only valid when the USB
Transmit Packet Count Enable field is set to one. Valid values are from 1 to 15.
23:16
0Ah
RW
USBMAXTXBURSTSIZE:
USB Maximum TX Burst Size: When USBTxPktCntSel is one,
this field specifies the Maximum Bulk OUT burst the core should do. When the system
bus is slower than the USB, TX FIFO can underrun during a long burst. User can
program a smaller value to this field to limit the TX burst size that the core can do. It
only applies to SS Bulk, Isochronous, and Interrupt OUT endpoints in the host mode.
Valid values are from 1 to 16.
15:11
0h
RO
GTXTHRCFG_RSVD2:
Reserved
10:0
0h
RW
GTXTHRCFG_RSVD1:
Reserved