Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2520

Datasheet

Default: 22800000h

Global Common Register

Default: 45803000h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GRXTHRCFG

_

RSV

D

3

US

BRXPKT

CN

TSEL

GRXTHRCFG

_

RSV

D

2

US

BRXPK

TCNT

USB

M

A

X

RXBURST

S

IZE

GRXTHRCFG

_

RSV

D

1

31:30

0h

RO

Reserved

29

1h

RW

USB ReceivePacket Count Enable: This field enables/disables the 

USB reception multi-packet thresholding: n 0: The core can only start reception on the 

USB when the RX FIFO has space for at least one packet. n 1: The core can only start 

reception on the USB when the RX FIFO has space for at least USBRxPktCnt amount of 

packets. This mode is only valid in the host mode. It is only used for SuperSpeed.

28

0h

RO

Reserved

27:24

2h

RW

USB Receive Packet Count: This field specifies space (in number of 

packets) that must be available in the RX FIFO before the core can start the 

corresponding USB RX transaction (burst). This field is only valid when the USB Receive 

Packet Count Enable field is set to one. The valid values are from 1 to 15.

23:19

10h

RW

USB Maximum Receive Burst Size: This field is only valid 

when USBRxPktCntSel is one. This field specifies the Maximum Bulk IN burst the core 

should do. When the system bus is slower than the USB, RX FIFO can overrun during a 

long burst. User can program a smaller value to this field to limit the RX burst size that 

the core can do. It only applies to SS Bulk, Isochronous, and Interrupt IN endpoints in 

the host mode. Valid values are from 1 to 16.

18:0

0h

RO

Reserved

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h