Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2717
20.6.21
CORBSTS—Offset 4Dh
CORB Status
Access Method
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
RE
S
E
R
V
E
D
0
ENAB
LE_C
ORB_DMA_E
N
GINE
CORB
_
M
E
M
O
R
Y_E
RROR_INTE
RRU
PT_E
NABLE
Bit
Range
Default &
Access
Description
7:2
00h
RO
RESERVED0:
reserved
1
0h
RW
ENABLE_CORB_DMA_ENGINE:
0 DMA Stop 1 DMA Run After SW writes a 0 to this bit
the HW may not stop immediately. The hardware will physically update the bit to a 0
when the DMA engine is truly stopped. SW must read a 0 from this bit to verify that the
DMA is truly stopped.
0
0h
RW
CORB_MEMORY_ERROR_INTERRUPT_ENABLE:
If this bit is set and GIE and CIE
are enabled the controller will generate an interrupt if the MEI status bit is set.
Type:
Memory Mapped I/O Register
(Size: 8 bits)
CORBSTS:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h